FIG. 1 shows the configuration of a conventional floating point arithmetic adder which performs floating point arithmetic of a finite word length digital signal. At first, let us consider a case where the absolute values of two inputs are very different from each other, in FIG. 1, e.g., when the absolute value of a first input 1 is much smaller than that of a second input 2. In this case, the value of the first input 1 is inputted from an input terminal 401, and the value of the second input 2 is inputted from an input terminal 402. Under such conditions, under flow of the first value is caused, namely, some amount of value of the first input 1 is omitted at the adder 403, thereby outputting a value which includes some amount of error to an output terminal 404. The main reason of this omission is the usage of floating point arithmetic with a finite length mantissa. Namely, since a finite digit number is used, the portions of a smaller input which are not included in the range of a larger number are neglected and the under flow is thus caused. The omitted portions causes errors.
Accordingly, the floating point arithmetic adder shown in FIG. 1 suffers from problems of accuracy in the floating point adding operation when the absolute values of two inputs are greatly different from each other. The following two examples is related to such problems about the accuracy in floating point adding operation.
FIG. 2 shows the configuration of a conventional integrator as a first example. Even in this case, when the absolute value of an input from an input terminal 501 is greatly smaller than that of a value of a memory circuit 503, the under flow sometimes occurs. FIG. 4 shows an output of the integrator when a constant value is continuously inputted, in which the axis of abscissa shows time t, and the axis of ordinate shows the output of the integrator. In the period from time 0 to time t.sub.1 of FIG. 4, the absolute value of the memory circuit 503 in the integrator of FIG. 2 is not so larger than that of the input value. Thus, no fatal under flow is caused. During this period, the floating point adder 502 outputs the floating point added result without fatal under flow, so that the value of the memory circuit 503 in the integrator proportionally increases in accordance with time. When the output of the integrator becomes very large in comparison with the input data, the under flow is caused from a certain time. When the under flow is caused from time t.sub. 1, the value of the memory circuit 503, which is the output of the integrator, after time t.sub.1 is not changed because of the under flow, thereby holding it at a constant value. The difference between the constant value and an ideal value of the output of the integrator designated by dotted line becomes large in accordance with time, and the accumulated error caused by the under flow becomes an infinite value after an infinite time has passed, thereby greatly reducing the accuracy of the integrator.
FIG. 3 shows the configuration of a second order loop filter often used in a conventional PLL(Phase Locked Loop). Even in this case, when the absolute value of an input from an input terminal 601 is greatly smaller than that of a value of a memory circuit 606, or when coefficients .alpha. 602 and .beta. 603 of the loop filter are very small, the input is not added exactly in adders 604 and 605, thereby causing under flow. The process of the under flow in the floating point adding operation is similar to the one in the integrator mentioned above.
In processing a digital signal, the error caused by under flow of the adder in the floating point arithmetic is a big problem. Thus, the integrator, the loop filer, etc. should have an adequate accuracy.
As mentioned above, in the adding apparatus which performs an addition of two input values with floating point, the under flow is caused when the difference between the absolute values of the two inputs is very large.